5G Layer 1 synchronisation for a hardware accelerator pipeline
Implemented accelerator synchronisation in 5G NR physical-layer baseband software that removed buffer stalls between processing stages, increasing throughput.
- Period
- 2025 — Present
- Client
- Telecom infrastructure (Ericsson)
- Role
- R&D Embedded Software Engineer
OutcomeBuffer sizes reduced and data handed off between stages without stalls — measurable throughput gain in the data path.
The problem
In 5G NR Layer 1, the baseband data path sits as close to the antenna as software gets. Samples arrive, get processed in stages — often by hardware accelerators on a proprietary ASIC — and leave the system on a hard deadline. If one stage finishes its work while the next is still reading its buffer, you either stall or you pay for a bigger buffer.
The pipeline had both problems: buffers sized generously to absorb the mismatch, and stalls when handover timing drifted.
Constraints
- Ultra-low latency. A few microseconds is a real regression, not an academic one.
- Proprietary ASIC semantics. The accelerator interfaces are documented, but their real timing behaviour has to be learned from hardware and simulation.
- Production code in a mature codebase. Changes are reviewed against existing behaviour on every other feature.
- Assembly where it counts. Some routines have to be hand-written for the internal accelerator ISA because the compiler will not meet the budget.
What I did
Implemented a synchronisation mechanism between accelerator stages so the handover point is explicit and verifiable rather than implicit in buffer size. That let the buffers shrink and removed the stalls.
Wrote custom Assembly routines for the internal accelerator architecture where the C compilation wasn’t tight enough for the timing budget.
Built the verification story alongside the feature — traffic and signalling configuration in simulation, then timing and data-integrity analysis on hardware. A timing feature is only as good as its measurement.
Trade-offs
- Explicit synchronisation over “big enough buffer”. Buffers are cheap in silicon and expensive in latency. Choosing correctness at the handover point costs a little control complexity and buys a lower floor on end-to-end delay.
- Hand-written Assembly only where measured. Every Assembly routine is a maintenance liability and a review burden. C first, Assembly where the profile says it matters.
Outcome
The feature delivered shorter buffers and smooth stage-to-stage handover, increasing system throughput, and shipped in the production Layer 1 codebase.
What I’d do differently
I’d have instrumented the pipeline for timing from day one. The first version needed more back-and-forth than it should have because I could see the result but not the cause.